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| W25X32A publication release date: august 7, 2009 - 1 - preliminary - revision b 32m-bit serial flash memory with 4kb sectors and dual output spi www.datasheet.co.kr datasheet pdf - http://www..net/
W25X32A - 2 - table of contents 1 ............................................................................................................... 4 general description 2 ....................................................................................................................................... 4 features 3 ............................................................................................ 5 pin configuration soic 208-mil 4 ...................................................................... 5 pad configuration wson 6x5-mm & 8x6-mm 5 .......................................... 5 pin description soic 208-mil, wson 6x5-mm, wson 8x6-mm 6 ............................................................................................ 6 pin configuration soic 300-mil 7 .................................................................................................. 6 pin description soic 300-mil 7.1 ..................................................................................................................... 7 package types 7.2 .................................................................................................................. 7 chip select (/cs) 7.3 ....................................................................................................... 7 serial data output (do) 7.4 ............................................................................................................... 7 write protect (/wp) 7.5 ..................................................................................................................... 7 hold (/hold) 7.6 ................................................................................................................ 7 serial clock (clk) 7.7 ........................................................................................... 7 serial data input / output (dio) 8 ............................................................................................................................ 8 block diagram 9 ......................................................................................................... 9 functional description 9.1 ............................................................................................................... 9 spi operations 9.1.1 ..............................................................................................................................9 spi modes 9.1.2 .....................................................................................................................9 dual output spi 9.1.3 .........................................................................................................................9 hold function 9.2 ....................................................................................................... 10 write protection 9.2.1 ..........................................................................................................10 write protect features 10 ........................................................................................ 11 control and status registers 10.1 .......................................................................................................... 11 status register 10.1.1 ............................................................................................................................... ...11 busy 10.1.2 ..................................................................................................11 write enable latch (wel) 10.1.3 ....................................................................................11 block protect bits (bp2, bp1, bp0) 10.1.4 ...........................................................................................11 top/bottom block protect (tb) 10.1.5 .....................................................................................................................11 reserved bits 10.1.6 ............................................................................................12 status register protect (srp) 10.1.7 ....................................................................................13 status register memory protection 10.2 ................................................................................................................. 14 instructions 10.2.1 ..............................................................................14 manufacturer and devi ce identification 10.2.2 ....................................................................................................................15 instruction set 10.2.3 ..............................................................................................................16 write enable (06h) 10.2.4 .............................................................................................................16 write disable (04h) www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A ................................................................................................17 publ ication release date: august 7, 2009 - 3 - preliminary - revision b 10.2.5 read status register (05h) 10.2.6 ................................................................................................18 write status register (01h) 10.2.7 .................................................................................................................19 read data (03h) 10.2.8 .................................................................................................................20 fast read (0bh) 10.2.9 .............................................................................................21 fast read dual output (3bh) 10.2.10 .........................................................................................................22 page program (02h) 10.2.11 ...........................................................................................................23 sector erase (20h) 10.2.12 ............................................................................................................24 block erase (d8h) 10.2.13 ..............................................................................................................25 chip erase (c7h) 10.2.14 ............................................................................................................26 power-down (b9h) 10.2.15 ...........................................................................27 release power-down / device id (abh) 10.2.16 ...............................................................................29 read manufacturer / device id (90h) 10.2.17 ................................................................................................................30 jedec id (9fh) 11 .............................................................................................. 31 electrical characteristics 11.1 ................................................................................................ 31 absolute maximum ratings 11.2 .............................................................................................................. 31 operating ranges 11.3 .................................................................... 32 power-up timing and write inhibit threshold 11.4 .............................................................................................. 33 dc electrical characteristics 11.5 ............................................................................................. 34 ac measurement conditions 11.6 .............................................................................................. 35 ac electrical characteristics 11.7 ................................................................................. 36 ac electrical characteristics (cont?d) 11.8 ........................................................................................................... 37 serial output timing 11.9 ........................................................................................................................ 37 input timing 11.10 ....................................................................................................................... 37 hold timing 12 .......................................................................................................... 38 package specification 12.1 ........................................................................... 38 8-pin soic 208-mil (package code ss) 12.2 .................................................................. 39 8-contact 6x5mm wson (package code zp) 8-contact 6x5mm wson cont?d. ................................................................................................... 40 12.3 .......................................................................... 41 16-pin soic 300-mil (package code sf) 12.4 .................................................................. 42 8-contact 8x6mm wson (package code ze) 13 .......................................................................................................... 43 ordering information 13.1 ........................................................................ 44 valid part numbers and top side marking 14 ...................................................................................................................... 45 revision history www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 4 - 1 general description the W25X32A (32m-bit) serial flash memory provi de a storage solution for systems with limited space, pins and power. the 25x series offers flexibilit y and performance well beyond ordinary serial flash devices. they are ideal for code download applications as well as storing voice, text and data. the devices operate on a single 2.7v to 3.6v power supply with current consumption as low as 5ma active and 1a for power-down. all devices ar e offered in space-saving packages. the W25X32A array is organized into 16,384 programmable pages of 256-bytes each. up to 256 bytes can be programmed at a time using the page program instruction. pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or t he entire chip (chip erase). the W25X32A has 1,024 erasable sectors and 64 erasable blocks. the small 4kb se ctors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the W25X32A supports the standard serial peripher al interface (spi), and a high performance dual output spi using four pins: serial clock, chip sele ct, serial data i/o and serial data out. spi clock frequencies of up to 100mhz are supported allowing equi valent clock rates of 200mhz when using the fast read dual output instruction. these transfer rates are comparable to those of 8 and 16-bit parallel flash memories. a hold pin, write protect pin and programmable write protect, with top or botto m array control features, provide further control flexibility. additionally , the device supports jedec standard manufacturer and device identification. 2 features ? family of serial flash memories ? W25X32A: 32m-bit / 4m-byte (4,194,304) ? 256-bytes per programmable page ? unif orm 4k-byte sectors / 64k-byte blocks ? spi with single or dual outputs ? clock, chip select, data i/o, data out ? optional hold function for spi flexibility ? data transfer up to 150m-bits / second ? clock operation to 100mhz ? fast read dual output instruction ? auto-increment read capability ? flexible architecture with 4kb sectors ? sector erase (4k-bytes) ? block erase (64k-byte) ? page program up to 256 bytes <2ms ? more than 100,000 erase/write cycles ? more than 20-year data retention ? low power consumption, wide temperature range ? single 2.7 to 3.6v supply ? 5ma active current, 1a power-down (typ) ? -40 to +85c operating range ? software and hardware write protection ? write-protect all or portion of memory ? enable/disable protection with /wp pin ? top or bottom array protection ? space efficient packaging ? 8-pin soic 208-mil ? 16-pin soic 300-mil ? 8-pad wson 6x5-mm ? 8-pad wson 8x6-mm (1) note 1 ? special order device package, please contac t winbond for more information about this package type. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 5 - preliminary - revision b 3 pin configuration soic 208-mil figure 1a. W25X32A pin assignments, 8-pin soic 208-mil (package code ss) 4 pad configuration wson 6x5-mm & 8x6-mm figure 1b. W25X32A pad assignments, 8-pad wson 6x 5-mm (package code zp) & 8x6-mm (package code ze) 5 pin description soic 208-mil, wson 6x5-mm, wson 8x6-mm pin no. pin name i/o function 1 /cs i chip select input 2 do o data output 3 /wp i write protect input 4 gnd ground 5 dio i/o data input / output 6 clk i serial clock input 7 /hold i hold input 8 vcc power supply www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 6 - 6 pin configuration soic 300-mil figure 1c. W25X32A pin assignments, 16-pin soic 300-mil (package code sf) 7 pin description soic 300-mil pin no. pin name i/o function 1 /hold i hold input 2 vcc power supply 3 n/c no connect 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do o data output 9 /wp i write protect input 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 dio i/o data input / output 16 clk i serial clock input www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 7 - preliminary - revision b 7.1 package types W25X32A is offered in an 8-pin plastic 208-mil wi dth soic (package code ss), 6x5-mm wson (package code zp), 16-pin plastic 300-mil width soic ( package code sf) and specal order 8x6-mm (package code ze). see figures 1a-c. package diagrams and dimensions are illustrated at the end of this datasheet. 7.2 chip select (/cs) the spi chip select (/cs) pin enables and disables the device operation. when /cs is high the device is deselected and the serial data output (do) pin is at high impedance. when deselected, the device?s power consumption will be at standby levels unless an inte rnal erase, program or st atus register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power-up (see ?write protection? and figure 20). if needed a pull-up resister on /cs can be used to accomplish this. 7.3 serial data output (do) the spi serial data output (do) pin provides a means for data and status to be serially read from (shifted out of) the device. data is shifted out on the falling edge of the serial clock (clk) input pin. 7.4 write protect (/wp) the write protect (/wp) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block pr otect (bp2, bp1, and bp0) bits and status register protect (srp) bits, a portion or the entire memory arra y can be hardware protected. the /wp pin is active low. 7.5 hold (/hold) the /hold pin allows the device to be paused while it is actively selected. when /hold is brought low, while /cs is low, the do pin will be at high impedanc e and signals on the dio and clk pins will be ignored (don?t care). when /hold is brought high, device operation can resume. the /hold function can be useful when multiple devices are sharing the same spi signals. (?see hold function?) 7.6 serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi operations") 7.7 serial data input / output (dio) the spi serial data input/output (dio) pin provi des a means for instructions, addresses and data to be serially written to (shifted into) the device. data is latched on the rising edge of the serial clock (clk) input pin. the dio pin is also used as an output pi n when the fast read dual output instruction is executed. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 8 - 8 block diagram figure 2. W25X32A serial fl ash memory block diagram 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h ? block 32 (64k 200000h ? ? ? 20ffffh b) ? 2000ffh 3fff00h ? block 63 (64k 3f0000h 3fffffh b) ? 3f00ffh column decode and 256-byte page buffer beginning page address ending page address W25X32A spi command & control logic byte address latch / counter status register write control logic page address latch / counter do dio /cs clk /hold /wp high voltage generators xx0f00h ? sector 0 (4kb) ? xx0000h xx00ffh xx0fffh xx1f00h ? xx1000h xx1fffh sector 1 (4kb) ? xx10ffh xx2f00h ? xx2000h xx2fffh sector 2 (4kb) ? xx20ffh ? ? ? xxdf00h ? xxd000h xxdfffh sector 13 (4kb) ? xxd0ffh xxef00h ? xxe000h xxefffh sector 14 (4kb) ? xxe0ffh xxff00h ? xxf000h xxffffh sector 15 (4kb) ? xxf0ffh blo ck segmentation data write protect lo gic and row decode 00ff00h 00ffffh ? block 0 (64kb) ? 000000h 0000ffh ? ? ? 0fff00h 0fffffh ? block 15 (64kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 31 (64kb) ? 1f0000h 1f00ffh 20ff00h ? block 32 (64k 200000h ? ? ? 20ffffh b) ? 2000ffh 3fff00h ? block 63 (64k 3f0000h 3fffffh b) ? 3f00ffh column decode and 256-byte page buffer beginning page address ending page address W25X32A spi command & control logic byte address latch / counter status register write control logic page address latch / counter do dio /cs clk /hold /wp high voltage generators xx0f00h ? sector 0 (4kb) ? xx0000h xx00ffh xx0fffh xx1f00h ? xx1000h xx1fffh sector 1 (4kb) ? xx10ffh xx2f00h ? xx2000h xx2fffh sector 2 (4kb) ? xx20ffh ? ? ? xxdf00h ? xxd000h xxdfffh sector 13 (4kb) ? xxd0ffh xxef00h ? xxe000h xxefffh sector 14 (4kb) ? xxe0ffh xxff00h ? xxf000h xxffffh sector 15 (4kb) ? xxf0ffh blo ck segmentation data write protect lo gic and row decode www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 9 - preliminary - revision b 9 functional description 9.1 spi operations 9.1.1 spi modes the W25X32A is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input/output (dio) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the prim ary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the dio pin is sampled on the rising edge of the clk. data on the do and dio pins are clocked out on the falling edge of clk. 9.1.2 dual output spi the W25X32A supports dual output operation when us ing the "fast read with dual output" (3b hex) instruction. this feature allows data to be transferr ed from the serial flash memory at twice the rate possible with the standard spi. this instruction is ideal for quickly downloading code from flash to ram upon power-up (code-shadowing) or for applications t hat cache code-segments to ram for execution. the dual output feature simply allows the spi input pin to also serve as an output during this instruction. all other operations use the standard spi interface with single output signal. 9.1.3 hold function the /hold signal allows the W25X32A operation to be paused while it is actively selected (when /cs is low). the /hold function may be useful in cases where t he spi data and clock signals are shared with other devices. for example, consider if the page buffer was only partially written when a priority interrupt requires use of the spi bus. in this case the /hold function can save the state of the instruction and the data in the buffer so programming can resume wher e it left off once the bus is available again. to initiate a /hold condition, the device must be selected with /cs low. a /hold condition will activate on the falling edge of the /hold signal if the clk signal is already low. if the clk is not already low the /hold condition will activate after the next falling edge of clk. the /hold condition will terminate on the rising edge of the /hold signal if the clk signal is already lo w. if the clk is not already low the /hold condition will terminate after the next falling edge of clk. during a /hold condition, the serial data output (do) is high impedance, and serial data input/output (dio) and serial clock (clk) are ignored. the chip sele ct (/cs) signal should be k ept active (low) for the full duration of the /hold operation to avoid resetting the inte rnal logic state of the device. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 10 - 9.2 write protection applications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise dat a integrity. to address this concern the W25X32A provides several means to protec t data from inadvertent writes. 9.2.1 write protect features ? device resets when vcc is below threshold. ? time delay write disable after power-up. ? write enable/disable instructions. ? automatic write disable after program and erase. ? software write protection using status register. ? hardware write protection using status register and /wp pin. ? write protection using power-down instruction. upon power-up or at power-down the W25X32A will ma intain a reset condition while vcc is below the threshold value of v wi , (see power-up timing and voltage levels and figure 20). while reset, all operations are disabled and no instructions are re cognized. during power-up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector eras e, block erase, chip erase and the write status register instructions. note that the chip select pi n (/cs) must track the vcc supply level at power-up until the vcc-min level and t vsl time delay is reached. if needed a pull-up resister on /cs can be used to accomplish this. after power-up the device is automatically placed in a write-disabled state with the status register write enable latch (wel) set to a 0. a write enable inst ruction must be issued before a page program, sector erase, chip erase or write status register inst ruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write stat us register instruction and setting the status register protect (srp) and block pr otect (tb, bp2, bp1, and bp0) bits. these status register bits allow a portion or all of the memory to be configured as read only. used in conjunction with the write protect (/wp) pin, changes to the stat us register can be enabled or disabled under hardware control. see status register for further information. additionally, the power-down instruction offers an extra level of write protection as all instructions are ignored except for the releas e power-down instruction. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 11 - preliminary - revision b 10 control and status registers the read status register instruction can be used to provide status on the av ailability of the flash memory array, if the device is write enabled or dis abled, and the state of writ e protection. the write status register instruction can be used to configure the devices write protection features. see figure 3. 10.1 status register 10.1.1 busy busy is a read only bit in the status register (s0) t hat is set to a 1 state w hen the device is executing a page program, sector erase, block er ase, chip erase or write status register instruction. during this time the device will ignore further in structions except for the read st atus register instruction (see t w , t pp , t se , t be , and t ce in ac characteristics). when the program, eras e or write status register instruction has completed, the busy bit will be cleared to a 0 state indi cating the device is ready for further instructions. 10.1.2 write enable latch (wel) write enable latch (wel) is a read only bit in the status register (s1) that is set to a 1 after executing a write enable instruction. the wel status bit is cleared to a 0 when the device is write disabled. a write disable state occurs upon power-up or after any of the following instructions: write disable, page program, sector erase, block erase, chip erase and write status register. 10.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, and bp0) are non-volatile read/write bits in the status register (s4, s3, and s2) that provide write protection control and stat us. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and erase instructions (s ee status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. the block protect bits can not be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 10.1.4 top/bottom block protect (tb) the top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the tb bit is non-volatile and the factory default setting is tb=0. the tb bit can be set with the write status register instruction provided that the write enable instruction has been issued. the tb bit can not be written to if the status register protect (srp) bit is set to 1 and the write protect (/wp) pin is low. 10.1.5 reserved bits status register bit location s6 is reserved for future use. current devices will read 0 for this bit location. it is recommended to mask out the reserved bit when test ing the status register. doing this will ensure compatibility with future devices. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 12 - 10.1.6 status register protect (srp) the status register protect (srp) bit is a non-volatile read/write bit in status register (s7) that can be used in conjunction with the write protect (/wp) pin to disable writes to status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control over status register. when the srp pin is set to a 1, the write status regist er instruction is locked out while the /wp pin is low. when the /wp pin is high the write status regist er instruction is allowed. figure 3. status register bit locations www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 13 - preliminary - revision b 1 0.1.7 s tatus register memory protection status register (1) W25X32A (32m-bit) memory protection tb bp2 bp1 bp0 block(s) addresses density portion x 0 0 0 none none none none 0 0 0 1 63 3f0000h ? 3fffffh 64kb upper 1/64 0 0 1 0 62 and 63 3e0000h ? 3fffffh 128kb upper 1/32 0 0 1 1 60 thru 63 3c0000h ? 3fffffh 256kb upper 1/16 0 1 0 0 56 thru 63 380000h ? 3fffffh 512kb upper 1/8 0 1 0 1 48 thru 63 300000h ? 3fffffh 1mb upper 1/4 0 1 1 0 32 thru 63 200000h ? 3fffffh 2mb upper 1/2 1 0 0 1 0 000000h ? 00ffffh 64kb lower 1/64 1 0 1 0 0 and 1 000000h ? 01ffffh 128kb lower 1/32 1 0 1 1 0 thru 3 000000h ? 03ffffh 256kb lower 1/16 1 1 0 0 0 thru 7 000000h ? 07ffffh 512kb lower 1/8 1 1 0 1 0 thru 15 000000h ? 0fffffh 1mb lower 1/4 1 1 1 0 0 thru 31 000000h ? 1fffffh 2mb lower 1/2 x 1 1 1 0 thru 63 000000h ? 3fffffh 4mb all note: 1. x = don?t care www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 14 - 10.2 instructions the instruction set of the W25X32A consists of fift een basic instructions that are fully controlled through the spi bus (see instruction set table). instructions ar e initiated with the falling edge of chip select (/cs). the first byte of data clocked into the dio input prov ides the instruction code. data on the dio input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and ma y be followed by address bytes, data bytes, dummy bytes (don?t care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diagram s for each instruction are included in figures 4 through 19. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (cs driven high after a full 8-bits have been clocked) otherwise the instructi on will be terminated. this feature further protects the device from inadvertent writes. additionally, wh ile the memory is being programmed or erased, or when the status register is being written, all inst ructions except for read status r egister will be ignored until the program or erase cycle has completed. 10.2.1 manufacturer and device identification manufacturer id (m7-m0) winbond serial flash efh device id (id7-id0) (id15-id0) instruction abh, 90h 9fh W25X32A 15h 3016h www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 15 - preliminary - revision b 10.2.2 instruction set (1) instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes write enable 06h write disable 04h read status register 05h (s7?s0) (1) (2) write status register 01h s7?s0 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) continuous fast read 0bh a23?a16 a15?a8 a7?a0 dummy (d7?d0) (next byte) continuous fast read dual output 3bh a23?a16 a15?a8 a7?a0 dummy i/o = (d6,d4,d2,d0) o = (d7,d5,d3,d1) (one byte per 4 clocks, continuous) page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) (next byte) up to 256 bytes block erase (64kb) d8h a23?a16 a15?a8 a7?a0 sector erase (4kb) 20h a23?a16 a15?a8 a7?a0 chip erase c7h power-down b9h release power- down / device id abh dummy dummy dummy (id7-id0) (4) manufacturer/ device id (3) 90h dummy dummy 00h (m7-m0) (id7-id0) jedec id 9fh (m7-m0) manufacturer (id15-id8) memory type (id7-id0) capacity notes: 1. data bytes are shifted with most si gnificant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the devic e on the do pin. 2. the status register content s will repeat continuously until /c s terminates the instruction. 3. see manufacturer and device identification table for device id information. 4. the device id will repeat continuously until /cs terminates the instruction. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 16 - 10.2.3 write enable (06h) the write enable instruction (figure 4) sets the write enable latch (wel) bit in t he status register to a 1. the wel bit must be set prior to every page pr ogram, sector erase, block erase, chip erase and write status register instruction. the write enable instruction is enter ed by driving /cs low, shifting the instruction code ?06h? into the data input (di) pi n on the rising edge of clk, and then driving /cs high. figure 4. write enable instruction sequence diagram 10.2.4 write disable (04h) the write dissable instruction (figure 5) resets the wri te enable latch (wel) bit in the status register to a 0. the write disable instru ction is entered by driving /cs low, shifting the instruction code ?04h? into the dio pin and then driving /cs high. no te that the wel bit is automatically reset after power-up and upon completion of the write status register, page pr ogram, sector erase, block erase and chip erase instructions. figure 5. write disable in struction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 17 - preliminary - revision b 10.2.5 read status register (05h) the read status register instructi on allows the 8-bit status register to be read. the instruction is entered by driving /cs low and shifting the instructi on code ?05h? into the dio pin on the rising edge of clk. the status register bits ar e then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 6. the status register bits are shown in figure 3 and include the busy, wel, bp2-bp0, tb and srp bits (see descr iption of the status register earlier in this datasheet). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction. the st atus register can be read continuously, as shown in figure 6. the inst ruction is completed by driving /cs high. figure 6. read status register instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 18 - 10.2.6 write status register (01h) the write status register instruction allows the status register to be written. a write enable instruction must previously have been exec uted for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is enter ed by driving /cs low, sending the instruction code ?01h?, and t hen writing the status register data byte as illustrated in figure 7. the status register bits are shown in fi gure 3 and described earlier in this datasheet. only non-volatile status register bits srp, tb, bp2, bp1 and bp0 (bits 7, 5, 4, 3 and 2) can be written to. all other status register bit locations are read-only and will not be affected by the write status register instruction. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the write status register instruct ion will not be executed. after /cs is driven high, the self-timed write status register cycle will comm ence for a time duration of t w (see ac characteristics). while the write status register cycle is in progre ss, the read status register instruction may still accessed to check the status of the busy bit. the busy bit is a 1 during t he write status register cycle and a 0 when the cycle is finished and ready to accept other instructions agai n. after the write regist er cycle has finished the write enable latch (wel) bit in the st atus register will be cleared to 0. the write status register instruction allows the bl ock protect bits (tb, bp2, bp1 and bp0) to be set for protecting all, a portion, or none of the memory fr om erase and program instructions. protected areas become read-only (see status register memory protection table). the wri te status register instruction also allows the status register protect bit (srp) to be set. this bit is used in conjunction with the write protect (/wp) pin to disable writes to the status register. when the srp bit is set to a 0 state (factory default) the /wp pin has no control ov er the status register. when the sr p pin is set to a 1, the write status register instruction is locked out while the /wp pin is low. when the /wp pin is high the write status register instruction is allowed. figure 7. write status register instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 19 - preliminary - revision b 10.2.7 read data (03h) the read data instruction allows one more data by tes to be sequentially read from the memory. the instruction is initiated by drivi ng the /cs pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the dio pin. the code and address bits are latched on the rising edge of the clk pin. after the address is re ceived, the data byte of the addre ssed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the address is automatically incremented to the next higher address afte r each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instru ction is completed by driving /cs high. the read data instruction sequence is shown in figur e 8. if a read data instruction is issued while an erase, program or write cycle is in process (bu sy=1) the instruction is ignored and will not have any effects on the current cycle. the r ead data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 8. read data instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 20 - 10.2.8 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics) . this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 9. the dummy clocks allow the devices internal circuits additional time for setting up the in itial address. during the du mmy clocks the data value on the dio pin is a ?don?t care?. figure 9. fast read instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 21 - preliminary - revision b 10.2.9 fast read dual output (3bh) the fast read dual output (3bh) in struction is similar to the standard fast read (0bh) instruction except that data is output on two pins, do and dio, instead of just do. this allows data to be transferred from the W25X32A at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power-up or for applications that cache code- segments to ram for execution. similar to the fast read instructi on, the fast read dual output in struction can operate at the highest possible frequency of f r (see ac electrical characteristics) . this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 10. the dummy clocks allow the device's internal circuits additional time for setting up the in itial address. the input dat a during the dummy clocks is ?don?t care?. however, the dio pin should be hi gh-impedance prior to the falling edge of the first data out clock. figure 10. fast read dual output instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 22 - 10.2.10 page program (02h) the page program instruction allows up to 256 bytes of data to be programmed at previously erased to all 1s (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit we l must equal 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code ? 02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the dio pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 11. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not zero, and the number of clocks exceed the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any e ffect on other bytes within the same page. one condition to perform a partial page program is that the number of clocks can not exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page progr am instruction will not be executed. after /cs is driven high, the self-timed page progr am instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the bu sy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and t he device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (we l) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). figure 11. page program instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 23 - preliminary - revision b 10.2.11 sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be exec uted before the device will a ccept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?20h? followed a 24-bit sector address (a23-a0) (see figure 2). the sector erase instruction sequence is shown in figure 12. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after /cs is driven high, the self-timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read stat us register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other inst ructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the stat us register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (tb, bp2, bp1, and bp0) bits (see status regist er memory protection table). figure 12. sector erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 24 - 10.2.12 block erase (d8h) the block erase instruction sets all memory within a specified block (64k-bytes) to the erased state of all 1s (ffh). a write enable instruction must be exec uted before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?d8h? followed a 24- bit block address (a23-a0) (see figure 2). the block erase instruction sequence is shown in figure 13. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self-timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status r egister instruction may still be access ed for checking the status of the busy bit. the busy bit is a 1 during the block eras e cycle and becomes a 0 when the cycle is finished and the device is ready to accept ot her instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is pr otected by the block protect (tb, bp2, bp1, and bp0) bits (see status register memory protection table). figure 13. block erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 25 - preliminary - revision b 10.2.13 chip erase (c7h) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?c7h?. the chip erase in struction sequence is shown in figure 14. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driv en high, the self-timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). while the chip erase cycle is in progress, the read status register instruction may still be a ccessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and bec omes a 0 when finished and the device is ready to accept other instructions again. a fter the chip erase cycle has finis hed the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any page is protected by the block protect (bp2, bp1, and bp0) bits (see status register memory protection table). figure 14. chip erase instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 26 - 10.2.14 power-down (b9h) although the standby current during nor mal operation is relatively low, standby current can be further reduced with the power-down instruction. the lower power consumption makes the power-down instruction especially useful for battery powered applic ations (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code ?b9h? as shown in figure 15. the /cs pin must be driven high after the eighth bi t has been latched. if this is not done the power-down instruction will not be executed. afte r /cs is driven high, the power-down state will entered within the time duration of t dp (see ac characteristics). while in the pow er-down state only the release from power- down / device id instruction, which restores the dev ice to normal operation, will be recognized. all other instructions are ignored. this incl udes the read status register instru ction, which is always available during normal operation. ignoring all but one instructi on makes the power down state a useful condition for securing maximum write protection. the device always powers-up in the normal operation with the standby current of icc1. figure 15. deep power-down instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 27 - preliminary - revision b 10.2.15 release power-down / device id (abh) the release from power-down / device id instructi on is a multi-purpose instruction. it can be used to release the device from the power-dow n state, obtain the devices electr onic identification (id) number or do both. when used only to release the device from the power-dow n state, the instruction is issued by driving the /cs pin low, shifting the instruction code ?abh? and driv ing /cs high as shown in figure 16. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the /cs pin must remain high during the t res1 time duration. when used only to obtain the device id while not in t he power-down state, the inst ruction is initiated by driving the /cs pin low and shifting the instruction c ode ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 17. the device id value for the W25X32A is listed in manufacturer and device identification table. the device id can be read continuously. the instru ction is completed by driving /cs high. when used to release the device from the power-down state and obtain the device id, the instruction is the same as previously described, and shown in figure 17, except that after /c s is driven high it must remain high for a time duration of t res2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from power-down / device id instructi on is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle figure 16. release power-down instruction sequence www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 28 - figure 17. release power-down / devi ce id instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 29 - preliminary - revision b 10.2.16 read manufacturer / device id (90h) the read manufacturer/device id instruction is an al ternative to the release from power-down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is in itiated by driving the /cs pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. afte r which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of cl k with most significant bit (msb) first as shown in figure 18. the device id value for the W25X32A is listed in manufacturer and device identification table. if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device id s can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 18. read manufacturer / device id diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 30 - 10.2.17 jedec id (9fh) for compatibility reasons, the W25X32A provides seve ral instructions to electronically determine the identity of the device. the read je dec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruct ion code ?9fh?. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 19. for memory type and capacity val ues refer to manufacturer and device identification table. figure 19. read jedec id instruction sequence diagram www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 31 - preliminary - revision b 11 electrical characteristics (1) 11.1 absolute maximum ratings (2) parameters symbol conditions range unit supply voltage vcc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to vcc +0.4 v transient voltage on any pin v iot <20ns transient relative to ground ?2.0v to vcc+2.0v v storage temperature t stg ?65 to +150 c lead temperature t lead see note (3) c electrostatic discharge voltage v esd human body model (4) ?2000 to +2000 v notes: 1. specification for W25X32A is preliminary. see preliminary designation at the end of this document. 2. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absol ute maximum ratings may affect device reliability. exposure beyond absolute maximum rati ngs may cause permanent damage. 3. compliant with jedec standard j-std-20c for sm all body sn-pb or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 4. jedec std jesd22-a114a (c1= 100 pf, r1=1500 ohms, r2=500 ohms). 11.2 operating ranges spec parameter symbol conditions min max unit supply voltage vcc f r0 = 75mhz, f r = 33mhz 2.7 3.6 v ambient temperature, operating t a industrial ?40 +85 c www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 32 - 11.3 power-up timing and write inhibit threshold spec parameter symbol min max unit vcc (min) to /cs low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1 2 v note: 1. these parameters are characterized only. figure 20. power-up timing and voltage levels www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 33 - preliminary - revision b 11.4 dc electrical characteristics spec parameter symbol conditions min typ max unit input capacitance c in (1) v in = 0v (2) 6 pf output capacitance cout (1) v out = 0v (2) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 25 50 a power-down current i cc 2 /cs = vcc, vin = gnd or vcc <1 10 a current read data / dual output read 1mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 5/6 7/8 ma current read data / dual output read 33mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 7/8 11/12 ma current read data / dual output read 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 9/10 13/15 ma current read data / dual output read 100mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 12/14 17/20 ma current page program i cc 4 /cs = vcc 20 25 ma current write status register i cc 5 /cs = vcc 10 18 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il ?0.5 vcc x 0.3 v input high voltage v ih vcc x0.7 vcc +0.4 v output low voltage v ol i ol = 1.6 ma 0.4 v output high voltage v oh i oh = ?100 a vcc ?0.2 v notes: 1. tested on sample basis and specified through desi gn and characterization data. ta=25 c, vcc 3v. 2. checker board pattern. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 34 - 11.5 ac measurement conditions spec parameter symbol min max unit load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 vcc to 0.8 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0.5 vcc to 0.5 vcc v note: 1. output hi-z is defined as the point where data out is no longer driven. figure 21. ac measurement i/o waveform www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 35 - preliminary - revision b 11.6 ac electrical characteristics spec description symbol alt min typ max unit clock frequency for all instructions, except read data (03h) 2.7v-3.6v vcc & industrial temperature f r0 f c0 d.c. 75 mhz clock frequency, for fast read (0bh, 3bh) only 3.0v-3.6v vcc & industrial temperature f r1 f c1 d.c. 100 mhz clock freq. read data instruction 03h f r d.c. 33 mhz clock high, low time for all instructions except read data (03h) t clh , t cll (1) 4.5 ns clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns /cs active hold time relative to clk t chsh 5 ns /cs not active setup time relative to clk t shch 5 ns /cs deselect time (for array read ? array read / erase or program ? read status register) t shsl t csh 50/100 ns output disable time t shqz (2) t dis 7 ns clock low to output valid 2.7v-3.6v / 3.0v-3.6v t clqv t v 7/6 ns output hold time t clqx t ho 0 ns continued ? next page www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 36 - 11.7 ac electrical characteristics (cont?d) spec description symbol alt min typ max unit /hold active setup time relative to clk t hlch 5 ns /hold active hold time relative to clk t chhh 5 ns /hold not active setup time relative to clk t hhch 5 ns /hold not active hold time relative to clk t chhl 5 ns /hold to output low-z t hhqx (2) t lz 7 ns /hold to output high-z t hlqz (2) t hz 12 ns write protect setup time before /cs low t whsl (3) 20 ns write protect hold time after /cs high t shwl (3) 100 ns /cs high to power-down mode t dp (2) 3 s /cs high to standby mode without electronic signature read t res 1 (2) 3 s /cs high to standby mode with electronic signature read t res 2 (2) 1.8 s write status register time t w 10 15 ms byte program time (first byte) (4) t bp1 30 50 s additional byte program time (after first byte) (4) t bp2 6 12 s page program time t pp 1.6 3 ms sector erase time (4kb) t se 120 200 ms block erase time (64kb) t be 0.32 1 s chip erase time t ce 20 40 s notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characte rization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when sector protect bit is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 37 - preliminary - revision b 11.8 serial output timing 11.9 input timing 11.10 hold timing www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 38 - 12 package specification 12.1 8-pin soic 208-mil (package code ss) millimeters inches symbol min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y - - 0.010 - - 0.004 0 - 8 0 - 8 notes: 1. controlling dimensions: millimeter s, unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d1 and e1 do not include mold flash protrusions and should be meas ured from the bottom of the package. 4. formed leads coplanarity with respect to seating plane shall be within 0.004 inches. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 39 - preliminary - revision b 12.2 8-contact 6x5mm wson (package code zp) ? millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.0275 0.0295 0.0314 a1 0.00 0.02 0.05 0.0000 0.0007 0.0019 b 0.35 0.40 0.48 0.0137 0.0157 0.0188 c - 0.20 ref. - - 0.0078 ref. - d 5.90 6.00 6.10 0.2322 0.2362 0.2401 d2 3.35 3.40 3.45 0.1318 0.1338 0.1358 e 4.90 5.00 5.10 0.1929 0.1968 0.2007 e2 4.25 4.30 4.35 0.1673 0.1692 0.1712 e (2) 1.27 bsc 0.0500 bsc l 0.55 0.60 0.65 0.0216 0.0236 0.0255 y 0.00 - 0.75 0.0000 - 0.0029 www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 40 - 8-contact 6x5mm wson cont?d. millimeters inches symbol min typ. max min typ. max solder pattern m 3.40 0.1338 n 4.30 0.1692 p 6.00 0.2360 q 0.50 0.0196 r 0.75 0.0255 notes: 1. advanced packaging information; please contact winbond for the latest minimum and maximum specifications. 2. bsc = basic lead spacing between centers. 3. dimensions d and e do not include mold flash protrusi ons and should be measured from the bottom of the package. 4. the metal pad area on the bottom center of the package is connected to the device ground (g nd pin). avoid placement of exposed pcb vias under the pad. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 41 - preliminary - revision b 12.3 16-pin soic 300-mil (package code sf) millimeters inches symbol min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 - 0.30 0.004 - 0.012 a2 - 2.31 - - 0.091 - b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 2 1.27 bsc 0.50 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y - - 0.076 - - 0.003 0 - 8 0 - 8 notes: 1. controlling dimensions: inches , unless otherwise specified. 2. bsc = basic lead spacing between centers. 3. dimensions d and e1 do not include mold flash protrusions and should be m easured from the bottom of the package. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 42 - 12.4 8-contact 8x6mm wson (package code ze) millimeters inches symbol min typ. max min typ. max a 0.70 0.75 0.80 0.02755 0.02952 0.03149 a1 0.00 0.02 0.05 0.0000 0.00078 0.00196 b 0.35 0.40 0.48 0.01377 0.01574 0.01889 c 0.19 .0.20 0.25 0.00748 0.00787 0.00984 d 7.90 8.00 8.10 0.31102 0.31496 0.31889 d2 4.60 4.65 4.70 0.18110 0.18307 0.18503 e 5.90 6.00 6.10 0.23228 0.23622 0.24015 e2 5.15 5.20 5.25 0.20275 0.20472 0.20669 e 1.27 bsc 0.05000 bsc l 0.45 0.50 0.55 0.01771 0.01968 0.02165 www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 43 - preliminary - revision b 13 ordering information (1) ss = 8-pin soic 208-mil sf = 16-pin soic 300-mil zp = 8-pad wson 6x5mm ze (2) = 8-pad wson 8x6mm v = 2.7v to 3.6v 32a = 32m-bit notes: 1a only the 2 nd letter is used for the part marking; wson pa ckage type zp is not used for the top marking. 1b. standard bulk shipments are in t ube (shape e). please specify alternate packing method, such as tape and reel (shape t), when placing orders. 1c. the ?w? prefix is not included on the part marking. 2. package type ze (wson-8 8x6mm) is a special order item, please contact winbond for availability. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A - 44 - 13.1 valid part numbers and top side marking the following table provides the valid part numbers for the W25X32A spiflash memory. please contact winbond for specific availability by density and package type. winbond spiflash memories use an 12- digit product number for ordering. however, due to limited space, the top side marking on all packages use an abbreviated 9 or 10-digit number depending on package type.. package type density product number top side marking ss soic-8 208mil 32m-bit W25X32Avssig 25x32avsig sf soic-16 300mil 32m-bit W25X32Avsfig 25x32avfig zp (1) wson-8 6x5mm 32m-bit W25X32Avzpig 25x32avig ze (1)(2) wson-8 8x6mm 32m-bit W25X32Avzeig 25x32avig notes: 1. for wson packages, the package type zp and ze are not used in the top side marking. 2. package type ze (wson-8 8x6mm) is a special order package, please c ontact winbond for ordering information. www.datasheet.co.kr datasheet pdf - http://www..net/ W25X32A publication release date: august 7, 2009 - 45 - preliminary - revision b 14 revision history version date page description a 08/24/08 all new create preliminary b 08/07/09 4, 5, 6 32, 34, 36, 40,43~45 changed references from 75mhz to 100mhz where appropriate. remove pdip8 added wson-8 8x6mm special order added wson-8 6x5mm update package diagrams updated ordering information preliminary designation the ?preliminary? designation on a winbond datasheet indicates that the product is not fully characterized. the specifications are subject to change and are not g ua ranteed. winbond or an authorized sales representative should be consulted fo r current information before using this product. trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical impl antation, atomic energy control in struments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, com bustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products coul d result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the right to make changes, corrections, modifications or improvements to this document and the products and services decribed herein at any time, without notice. www.datasheet.co.kr datasheet pdf - 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